Space‐Efficient Logical Qubit Architecture with a Bus for Magic State Consumption

ABSTRACT We propose a logical qubit architecture for quantum computing systems with quantum error correction codes, considering the consumption of magic states. The path to the magic state is represented as a bus, and two types of architecture using a single‐line bus, which uses physical qubits encoded with a repetition code, are presented. The architecture with the single‐line bus minimizes the number of physical qubits, which refers to the space cost. In addition, the increase in the time cost owing to the single‐line bus is mitigated by introducing scheduling and routing algorithms. Using simulations of benchmarks, we compared the costs of the proposed architecture with those of a full‐patch architecture, which uses only ancilla patches. The space cost is significantly reduced, offsetting the increase in the time cost and decreasing the space–time cost of some benchmarks. We also estimate the logical error rate of each architecture, and the proposed architecture achieves at least 10 times higher logical error rate than the full‐patch architecture at the same distance. However, the proposed architecture can improve the error rate by using higher distances with a slightly increased physical qubit budget. Therefore, it is feasible for near‐term quantum computers with approximately 10000–40000 qubits.