PERFORMANCE ANALYSIS OF SQUARE ROOT EVALUATOR USING ANCIENT INDIAN MATHEMATICS

Square root is vital operation in many computer graphics applications and scientific calculation processors. The growing demand for faster calculation of arithmetic operations and the power consumption leads to the analysis of square root using ancient Indian techniques and also implementation on hardware. This paper focuses on designing and analysis report of square root algorithm based on ancient Indian mathematics i.e. Vedic mathematics. Vedic mathematics is well known for its finding faster results, both for mental calculation and hardware design. The square root for 8-bit input has been implemented on Xilinx Spartan-6 FPGA. The synthesis report shows number LUTs used and combinational delay which is efficient in term of area and speed as compared to conventional methods.