Power Efficiency in Unfolding RIPEMD-160: Dynamic Power Analysis Using Gray Encoding in FPGA Design

Abstract The RIPEMD-160 hash functions are extensively used in many cryptographic applications, including digital signatures, Hash Message Authentication Codes (HMAC) and others. Unfolding RIPEMD-160 was designed to analyse the architecture of the design in terms of ALUTs area and design speed. This method was also applied to RIPEMD-160 designs to analyse the internal structure concerning area, maximum frequency, and throughput. The implementation of design using the unfolding transformation approach with a factor of four yields significant throughput performance. This project aims to enhance the power efficiency of the RIPEMD-160 hash function with an unfolding factor of 4 through the application of Gray encoding. The unfolding transformation factor of four approaches can increase RIPEMD-160’s throughput to approximately 1753.50 Mbps. The performance-to-area ratio of RIPEMD-160, when unfolded with factor four designs, exhibits an increase of 1.51% relative to the iterative RIPEMD-160 design. The design was simulated to verify the accuracy of the RIPEMD-160 designs regarding functional and timing simulations. The dynamic power consumption of the RIPEMD-160 design using Gray encoding was reduced by 64.6% compared to binary encoding and this is attributed to the lower switching activity associated with Gray encoding.