An Efficient LBlock Lightweight Block Cipher Coprocessor on RISC-V: Combinational Key Schedule Fusion and S-Box-to-LUT Mapping

Resource-constrained Internet-of-Things (IoT) terminals require encryption engines that combine low silicon cost with adequate throughput, a balance that is hard to reach with general-purpose software alone. This paper presents an LBlock lightweight block cipher coprocessor tightly coupled to an open-source RISC-V (Hummingbird E203) core through the NICE custom-instruction interface. LBlock serves here as a compact Feistel-cipher benchmark targeting legacy and low-volume IoT deployments rather than as a substitute for newer standards such as ASCON. We exploit two structural properties of LBlock: first, its 4-bit S-boxes map naturally onto the six-input look-up tables (LUTs) of modern FPGAs, so the entire substitution layer is realized as eight parallel single-LUT-depth tables instead of multi-cycle table lookups. Second, the LBlock key schedule is a one-way feedback-free recurrence, which lets us refactor key expansion from an independent multi-cycle sequential module into a pure combinational function that is fused with the round function and executed in the same clock cycle. The resulting encryption core performs one round per cycle, reducing core-only single-block latency from 226 cycles in the baseline implementation to 34 cycles, while the complete NICE coprocessor operation requires 85 cycles including data movement, instruction issue, computation, and write-back. The design is described in Chisel and integrated as a coprocessor with three custom instructions. On an FPGA-based SoC, the coprocessor produces outputs identical to the LBlock test vectors and accelerates encryption by 121.45× over a software baseline on the same core, while the encryption core reaches 321.7 MHz (643 Mbps) on Artix-7 and up to 472.2 MHz (944 Mbps) on Virtex-7 while occupying only 187 LUTs, as validated across three FPGA families. These results show that matching the algorithmic symmetry of LBlock to the underlying hardware fabric yields a lightweight and low-overhead cryptographic accelerator suitable for RISC-V IoT endpoints.