Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors

This study presents a formal approach to designing pipelined arithmetic circuits over Galois fields (GFs). The proposed method extends a graph-based circuit description known as a Galois-field arithmetic circuit graph (GF-ACG) to Linear-time Temporal Logic (LTL) in order to represent the timing property of pipelined circuits. We first present the extension of GF-ACG and its formal verification using computer algebra. We then demonstrate the efficiency of the proposed method through an experimental design of a lightweight cryptographic processor. In particular, we design a tamper-resistant datapath with threshold Implementation (TI) based on pipelining and multi-party computation. The proposed method can verify the processor within 1 h, whereas conventional methods would fail.