An ASIC implementation of low area AES encryption core for wireless networks

This paper presents an efficient ASIC implementation of the low area 8-bit AES encryption core using an optimized SBox for wireless networks. The proposed AES core supports 128- bit key length and 128-bit data blocks. The implementation results in a 90nm CMOS standard library show that the proposed AES encryption core has the maximum clock frequency of 452.5 MHz and higher resource usage efficiency compared with other designs.