Analysis of Ternary logic arithmetic circuits

<em>Complementary metal oxide semiconductor (CMOS) technology has facing a problems when down scaling a device. However, CMOS have the limitations in lower technology,</em> <em>to avoid the drawbacks of CMOS researchers have introduced the carbon nan-tube FETS (CNTFETs).</em><em> CNTFETs have the flexibility to</em> <em>change</em> <em>the</em> <em>threshold</em> <em>voltage</em> <em>of the device </em><em>by</em> <em>changing the device</em> <em>dimensions </em> <em>such as length and width. Hence this property of the CNTFET is useful for designing of multi-valued logic</em> <em>(MVL) such as ternary logic. These types of MVL logical circuits are useful for reduction in the hardware of the circuit. Hence, it can be reduce the wiring connection complexity</em> <em>compared to</em> <em>that of other digital logic circuits. This paper presents a CNTFET based ternary arithmetic circuits for the improvement of device complexity because all arithmetic digital circuits are play a major role in many electronic applications. We have verified the functionality of ternary half adder by using CNTFET. All the simulations have done in HSpice using 32nm technology node. </em>