Efficient FPGA Implementation of RSA Algorithm Using Vedic Multiplier

Technology cannot function effectively and securely without algorithms, which also enable integrity and encryption. To secure sensitive data, especially when it is delivered over an unsecured network like the Internet, we employ the RSA (Rivest-Shamir-Adleman) Algorithm, which forms the backbone of the cryptosystem that permits public key encryption. In a cryptosystem, multipliers are essential since they help to produce the desired results as efficiently as possible. The enormous number of adders and other digital circuits used in typical multipliers causes an increase in propagation delay, which eventually reduces the multiplier's efficiency. In contrast, the Vedic Multiplier can overcome this issue and operates at high efficiency. The objective is to develop an effective 8 X 8 Vedic multiplier and implement it in the Field Programmable Gate Array (FPGA) using the simulation tool Xilinx - ISE Design Suite 14.7. The effective performance metrics are compared with the pre-existing booth multiplier in terms of combinational path delay, number of slices, and number of Look Up Table (LUT)s. Further, the Modular exponentiation operation in RSA cryptosystem is replaced with the proposed Vedic multiplier and booth multiplier logics. The effectiveness of the RSA implementation with these operator logics is compared in terms of delay and area.