Efficient Configurable Digit-Serial Multiplier Based on Improved Karatsuba Algorithm over GF(2m)

The core operation of public key cryptosystems such as Elliptic Curve Cryptography (ECC) is modular multiplication. In recent years, designing high-performance multipliers for simplifying circuit structure, reducing hardware area, and improving computational efficiency has become a research hotspot. In this paper, a digit-serial least significant digit (LSD) modular multiplier with pipelined structure is proposed based on the block recombination Karatsuba Algorithm (BRKA). Moreover, by converting the data form of the multiplication operands, we can meet the operational requirements of irreducible polynomials in any field, and achieve the purpose of configurability. From theoretical analysis and synthesis results, compared with the better related work, the proposed multiplier not only meets the operation requirements of various domain-valued ECC algorithms, but also achieves a 20.52%reduction in time, 8.82% savings in area consumption, and provides 27.53% saving of area-delay product (ADP).