A High-Performance and Reconfigurable Hardware Architecture for FrodoKEM

FrodoKEM is an unstructured lattice-based post-quantum key encapsulation mechanism (KEM) renowned for its minimal algebraic structure and conservative security guarantees, offering strong confidence in long-term security. Building on these characteristics, the scheme is on track for standardization by ISO/IEC. However, research on full hardware acceleration has been limited because FrodoKEM’s core matrix multiplication lacks an efficient fast computation method and suffers from low data-level parallelism, which hinders its widespread adoption. To overcome this challenge, we present a fully hardware-optimized architecture that accelerates FrodoKEM on FPGA. Our design features a new block-by-block matrix multiplication algorithm that increases data-level parallelism to 28×, a time-multiplexed three-BRAM architecture with intra- and inter-phase sharing to minimize storage, an instruction-based finite state machine (FSM) for flexible control of irregular memory accesses, and a unified reconfigurable datapath that supports all FrodoKEM parameter sets under a single hardware implementation. As a result, implemented on a Xilinx Artix-7 FPGA, our design achieves throughput improvements of 23.4x, 22.1x, and 19.8x for KeyGen, Enc, and Dec at NIST security level 1, and 24.6x, 23.3x, and 21.5x at level 3, compared to comparable implementations. Moreover, our design attains the lowest area-time product (ATP), demonstrating superior area-time efficiency.