FPGA-Based CNN Acceleration Algorithm Design Using Diffused Convolution and Pruning Techniques

Convolutional Neural Networks (CNNs) have emerged as a critical tool in computer vision, and FPGA-based acceleration has become a primary approach for the efficient deployment and implementation of CNNs. In this paper, we propose an FPGA-accelerated CNN design that leverages diffused convolution and pruning techniques to significantly enhance computational efficiency. By reordering the convolution operations in the convolutional layers and optimizing the data flow, our approach reduces idle computation time, thereby improving the overall efficiency of the convolution process. Additionally, the pruning technique is employed to eliminate redundant weights in the network, which not only reduces computational complexity but also minimizes memory usage, further accelerating the CNN. Experimental results demonstrate that our proposed method achieves a 220% speedup compared to traditional FPGA-based CNN implementations, while maintaining an accuracy of over 98.23%.