article
Open access
CHERI: Hardware-Enabled C/C++ Memory Protection at Scale
Research footprint
At a glance
- Citations
- 9
- References
- 11
- Comments
- 0
Paper overview
Abstract
The memory-safe Capability Hardware Enhanced RISC Instructions (CHERI) C and C++ languages build on architectural capabilities in the CHERI protection model. With the development of two industrial CHERI-enabled processors, Arm’s Morello and Microsoft’s CHERIoT, CHERI may offer the fastest path to widely deployed memory safety.
Record transparency
Publication details
- DOI
- 10.1109/msec.2024.3396701
- OpenAlex
- W4399881573
- Document type
- article
- Language
- EN
- Source
- IEEE Security & Privacy
- Last metadata update
Comments
Log in to join the discussion.