Manvi Jha

OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design

2025

OpenRTLSet1introduces the largest fully open-source dataset for hardware design, offering over 127,000 diverse Verilog code samples to the research community and industry. Our dataset uniquely combines Verilog code from GitHub repositories (98k modules), VHDL translations …