Neil Hanley

Pre-processing power traces to defeat random clocking countermeasures

2015

We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the …

Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption

2015 · IEEE Transactions on Computers

Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is …