The Basic Model of Attack Resistance Estimation for Monitoring the Program Code Integrity of the FPGA-Based Systems

An approach to monitoring the program code integrity of FPGA-based systems is considered. The approach is based on the use of a digital watermark to store monitoring information. As part of this approach, an integrity monitoring method is considered, which is characterized by the use of several rounds of the embedding of a digital watermark in a program code. A basic model for estimation the complexity of the attack on the integrity monitoring method is proposed. The model takes into account the possible directions of attack, both related to the storage of monitoring information in the form of a digital watermark, and the direction of attack due to the traditional mechanisms for protection of the method. With the help of the proposed model, the stages of the attack, which appear during the transition from traditional methods of storing control information to its storage in the form of a digital watermark, are shown.