Evaluation of the Design Exploration of a Binarized Neural Network for FPGA using HDLRuby

This paper presents an example of design exploration using the hardware description language HDLRuby of a binarized neural network (BNN) targeting a FPGA. It took 21 hours for describing and testing down to the FPGA mapping a BNN circuit that is customized directly from the result of offline software training. The description in HDLRuby has a total of 714 lines of code for any possible BNN architecture, while the same hardware reimplemented in Verilog HDL code requires 1107 lines of code for a single BNN architecture. Mapped on a FPGA, the BNN with an optimal structure of one inner layer with 256 neurons succeeded in computing one result per cycle, for a power consumption lower than 6.5W.