Ph.D. Project: A Novel Compilation-Based Approach for Generating Sparse Tensor Accelerators

Sparse tensor computing is widely used in deep learning and scientific computing, but its irregularity challenges GPU/NPU acceleration. FPGAs, with their reconfigurability, are well-suited for sparse workloads. However, current point-wise, manual design methodologies significantly limit the performance potential of reconfigurable hardware across diverse sparse scenarios. This paper proposes a compiler framework that automatically generates high-performance sparse accelerators on FPGA. It includes: (1) a schedule-primitive-based DSL serving as sparse accelerator design specification, covering a wide range of design concerns; (2) a two-stage mapping mechanism based on sparse meta-operations, enabling flexible mapping from arbitrary sparse dataflow to hardware microarchitectures; and (3) a heuristic design space exploration strategy guided by workload characteristics.