A Cost-Sensitive and Simple Masking Design for Side-Channels

Conventional countermeasures against Power Analysis Attacks ignore area overhead for implementation since it only pursuit perfect tamper-resistance. While the countermeasures achieve high tamper-resistance, unacceptable area overhead is required. Thus, the design of the countermeasures cannot be applied for IoT edge devices, which are provided as cheaper products. In this paper, first, we show the unacceptable area overhead by the conventional countermeasures, then propose a lightweight and fundamental VLSI design method against Power Analysis Attack. Masked Wave Flip-Flop (MW-FF), proposed design method achieves higher tamper-resistance than Wave Dynamic Differential Logic (WDDL) that is one of the conventional countermeasures with small and acceptable area overhead. Our evaluations show that MW-FF requires only 12.51% and 5.89% of are overhead in FPGA and ASIC respectively, which is 114.03% and 21.82% saved comparing with WDDL.