Performance characterization of a multi-module quantum processor with static inter-chip couplers

Abstract Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of $9 \times 10^{-3}$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mn>9</mml:mn> <mml:mo>×</mml:mo> <mml:msup> <mml:mn>10</mml:mn> <mml:mrow> <mml:mo>−</mml:mo> <mml:mn>3</mml:mn> </mml:mrow> </mml:msup> </mml:math> in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of $6 \times 10^{-4}$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mn>6</mml:mn> <mml:mo>×</mml:mo> <mml:msup> <mml:mn>10</mml:mn> <mml:mrow> <mml:mo>−</mml:mo> <mml:mn>4</mml:mn> </mml:mrow> </mml:msup> </mml:math> , consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of $7 \times 10^{-3}$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mn>7</mml:mn> <mml:mo>×</mml:mo> <mml:msup> <mml:mn>10</mml:mn> <mml:mrow> <mml:mo>−</mml:mo> <mml:mn>3</mml:mn> </mml:mrow> </mml:msup> </mml:math> extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors.