UVM Verification of RISC-V Instruction set

This paper introduces a comprehensive verification methodology tailored specifically for RISC-V processors, leveraging the power of the Universal Verification Methodology (UVM). With its open standard architecture, RISC-V stands out for its simplicity and efficiency, making it a preferred choice across diverse application domains. The utilization of UVM, a suite of standard tools and APIs, enhances the robustness of the verification process for RISC-V designs and Systems on Chip (SoCs). The proposed methodology encompasses various critical aspects, including the design of testbenches, implementation of agents, generation of stimuli, and adoption of coverage-driven verification techniques. Through meticulous execution of tests, careful monitoring of instruction flows, and comprehensive summaries of simulation results, the study showcases the effectiveness and reliability of the proposed methodology in thoroughly scrutinizing RISC-V processors. This approach not only ensures the correctness and reliability of RISC-V designs but also sets a standard for future verification strategies, potentially leading to advancements in the verification process for emerging architectures.