Aspycot: A Spike and Python Co-simulation Testbench for Hardware Monitoring IPs

As systems-on-chip (SoCs) scale in complexity, monitoring Intellectual Properties (IPs) such as trace components, performance monitoring units (PMUs), and security-related IPs have an essential role in providing insights on the system real-time behavior, allowing for more efficient debugging, performance analysis, and security assurance.In this work, we present a methodology to rapidly prototype and validate hardware monitoring IPs at the pre-silicon stage, by abstracting the rest of the system.The methodology relies on an instruction set simulator (ISS) to generate trace of executed applications and on tools to simulate these traces on the IPs.We propose a platform incorporating this methodology, called Aspycot.It leverages established projects from the open-source hardware community and is designed to be as modular and straightforward as possible.To illustrate the interest and efficiency of Aspycot, we present a case study related to control-flow monitoring to a single core architecture.